Referring first to FIG. 1, a conventionally configured computer system 1 will now be described in greater detail. As may now be seen, the computer system 1 includes a digital signal processing (or “DSP”) sub-system 2 and plural system devices 3-1 through 3-n, all of which are coupled to system bus 4. It should be clearly understood, however, that, as illustrated in FIG. 1, both the computer system 1 and the various components thereof have been greatly simplified for ease of description. For example, in addition to DSP core 2a, the DSP sub-system 2 will typically include a number of other components, for example, interface logic circuit, one or more memory devices for storing instructions and/or data, and one or more peripheral devices, omitted from FIG. 1 for ease of illustration. The DSP sub-system 2, as well as each one of the system devices 3-1 through 3-n are capable of accessing the system bus 4, for example, to perform a read operation from a peripheral memory device. Competing accesses to the system bus 4, for example, an access to the system bus 4 by the system device 3-1 and an access to the system bus 4 by the DSP sub-system 2, are handled by system arbiter 10.
As DSP applications became more complex, however, computer systems began requiring greater processing power than that available by employing the computer system 1. One solution to this demand for greater processing power may be seen in FIG. 2. As may now be seen, the computer system 1 has been modified by adding additional DSP sub-systems thereto. More specifically, FIG. 2 shows a multiple-DSP computer system 5 having a first DSP sub-system 7-1, a second DSP sub-systems 7-2 and plural system devices 8-1 through 8-n, all of which are coupled to the system bus 6. It should again be noted that both the computer system 5 and the various components thereof have been greatly simplified for ease of description. As before, each of the first and second DSP sub-system 7-1 and 7-2, as well as each one of the system devices 8-1 through 8-n are capable of accessing the system bus 6, for example, to perform a read operation from a peripheral memory device. Competing accesses to the system bus 6, for example, an access to the system bus 6 by the system device 8-1 and an access to the system bus 6 by the first DSP sub-system 7-1, are handled by system arbiter 9.
While the dual DSP sub-systems provides the computer system 5 with greater processing power when compared to the computer system 1, the solution shown in FIG. 2 is not without its drawbacks as well. More specifically, the bandwidth of the system bus 6 is now the limiting factor for the overall performance of the computer system 5. Bandwidth becomes of particular concern when the computer system 5 is an asynchronous system, for example, when the first and second DSP sub-systems 7-1 and 7-2 run at a first clock speed while the system devices 8-1 through 8-n run at a second, slower, clock speed. In such a system, the ability of the faster first and second DSP sub-systems 7-1 through 7-2 to complete transactions would be adversely affected by the slower system devices 8-1 through 8-n.
What is needed, therefore, is a multiple-DSP computer system configured to enable the DSP sub-systems thereof to function independently using only the resources of buses local to those DSP sub-systems. By doing so, traffic on a global bus of the multiple-DSP computer system would be reduced, thereby enhancing performance of the multiple DSP computer system.